Method for power capping with co-operative dynamic voltage and frequency scaling via shared p-state table
US8001402B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2007 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Mar 16, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A co-operative mechanism in which a service processor and a host CPU (with an as running thereupon) work together to implement both power capping and utilization-based power savings, and with negligible side effects. Preferably, a 2-level modulation scheme is employed to undertake both power capping and energy savings simultaneously. Preferably, a frequency governor in the as running on a host processor saves power by modulating p-states based on a shared table, thus avoiding SMIs. The range of the p- I states in the shared table is adjusted to implement power capping in conjunction with power sensors in the system. This adjustment can be done either by a service processor, which can monitor total energy consumption, or an as or software running on the host processor, which can read energy consumption from the service processor and adjust the shared table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.