Memory board with self-testing capability
US8001434B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2009 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Aug 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.