Process for fabricating a high-integration-density image sensor
US8003433B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2007 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Apr 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/026
Abstract
The present application relates to the fabrication of an electronic component. The component comprises two, superposed integrated circuits: one of which is formed on the front side of a thinned first substrate, and the other of which is produced on the front side of a second substrate, with an insulating planarization layer interposed between the front sides of the two substrates. The silicon of the backside of the thinned substrate is opened locally above a first conducting area located in the thinned substrate and above a second conducting area located in the second substrate. A conducting layer portion, deposited on both areas, electrically connects them so as to provide the interconnection between the two circuits. The external connection pads may also be formed in this conducting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.