Self-aligned process for nanotube/nanowire FETs
US8003453B2 · kind B2 · utility
10Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2008 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Aug 8, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.