Methods of manufacturing semiconductor device having recess channel array transistor
US8003464B2 · kind B2 · utility
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2References
21Claims
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Key dates
| Filing date | Jun 17, 2008 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Aug 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/664
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of manufacturing a semiconductor device having an RCAT are provided. The method includes forming a first recess having a first depth formed in an active region of a semiconductor substrate, and a second recess having a second depth that is less than the first depth formed in an isolation layer. The depth of the second recess is decreased by removing the isolation layer from the upper surface of the isolation layer by a desired thickness. A gate dielectric layer is formed on an inner wall of the first recess and a gate is formed on the gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.