Semiconductor integrated circuit device having metal interconnect regions placed symmetrically with respect to a cell boundary
US8004014B2 · kind B2 · utility
4Cited by
5References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2009 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Aug 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.