PLL control circuit
US8004323B2 · kind B2 · utility
0Cited by
2References
15Claims
0Family size
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Inventors
Key dates
| Filing date | Nov 1, 2006 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Aug 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL control circuit, which outputs a PLL clock in response to a reference clock, is provided with a frequency adjustment circuit which performs frequency adjustment such that the PLL clock frequency is substantially constant even when the reference clock varies. The frequency adjustment circuit changes a set value in a counter, which determines the PLL clock frequency, in accordance with the variation in the reference clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.