Digital charge pump PLL architecture
US8004326B2 · kind B2 · utility
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10References
22Claims
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Key dates
| Filing date | Dec 13, 2007 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Dec 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/103
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.