Voltage regulator for memory
US8004924B2 · kind B2 · utility
13Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2009 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Feb 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference is regulated at the highest threshold voltage between pull-up and pull-down transistors of a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.