Ethernet controller
US8004988B2 · kind B2 · utility
1Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2007 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Aug 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/30
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An Ethernet controller has a buffer memory for receiving data packets, a data flow control unit for controlling the data flow to Ethernet controller, a packet counter, packet counter control logic for incrementing and decrementing the packet counter, a first register for storing a watermark, and a comparator logic coupled to the packet counter and the register for sending control signals to the data flow control unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.