System and method for mitigating the effects of bit insertion in a communications environment
US8005116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2006 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Aug 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W88/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for communicating data is provided that includes receiving a plurality of bits associated with a communications flow and determining whether one or more samples included in the flow should be suppressed. The method also includes suppressing a selected one or more of the samples if the selected samples are similar to previously received samples. The cell site element is further operable to invert one or more selected header bits. In a more particular embodiment, the bits to be inverted are part of a fixed length field and the inverted bits are odd. The inversion of the bits reduces packet overhead that is present in an HDLC communications environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.