Half width counting leading zero circuit
US8005880B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2007 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | May 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method are provided for storing a data word in a latch and determining the number of consecutive equal value bits within the data word. The data word consists of bits stored in unique bit positions and having a least significant bit position and a most significant bit position. The data word is examined to determine the number of consecutive bits having the same numeric value. The invention first corrects for any single bit anomaly within the consecutive equal value sequence, counts the number of consecutive bits having this equal value using logic that examines only every other bit position of the stored data word and provides a numeric value representing this number of consecutive equal value bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.