Dynamically allocated store queue for a multithreaded processor
US8006075B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 2009 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Feb 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/383
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for storage of writes to memory corresponding to multiple threads. A processor comprises a store queue, wherein the queue dynamically allocates a current entry for a committed store instruction in which entries of the array may be allocated out of program order. For a given thread, the store queue conveys store data to a memory in program order. The queue is further configured to identify an entry of the plurality of entries that corresponds to an oldest committed store instruction for a given thread and determine a next entry of the array that corresponds to a next committed store instruction in program order following the oldest committed store instruction of the given thread, wherein said next entry includes data identifying the entry. The queue marks an entry as unfilled upon successful conveying of store data to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.