Efficient encoding and decoding methods for representing schedules and processing forward error correction codes
US8006160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Jun 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3761
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sequence of symbol operations (a “schedule representation”) within a data storage device, wherein the operations are those used to process encoding or decoding operations of a forward error correction code (an “FEC code”) upon an arbitrary block of data of a given size (where size can be measured in numbers of symbols). The method is such that the schedule representation can be used to direct the processing of these operations upon a block of data in a way that is computationally efficient. Preferably, the same method can be applied to represent schedules derived from multiple different algorithms for the encoding or decoding of a code or for multiple different codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.