Semiconductor device layout method, a computer program, and a semiconductor device manufacture method
US8006205B2 · kind B2 · utility
61Cited by
18References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 6, 2007 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Feb 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device layout method is disclosed, wherein vias carrying the same signal are arranged at intervals equal to the minimum value defined by a design rule, and vias carrying different signals are arranged at second intervals that are greater than the minimum value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.