Semiconductor device including a plurality of diffusion layers and diffusion resistance layer
US8008723B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 2009 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Mar 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffusion layers formed in the well, and a diffusion resistance layer formed in the well, wherein the first diffusion layers have a second conductivity type, and are connected in parallel with each other to an input/output terminal of the semiconductor device; the second diffusion layers are arranged alternately with a plurality of first diffusion layers, and are connected to a power source or to the ground; the diffusion resistance layer has a second conductivity type, and is located in adjacent to any of the plurality of second diffusion layers; the diffusion resistance layer is connected to the input/output terminal of the semiconductor device, while being arranged in parallel with the first diffusion layers, and connects the internal circuit and the input/output terminal of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.