Memory access strobe configuration system and process
US8009491B2 · kind B2 · utility
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Key dates
| Filing date | Nov 6, 2009 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Nov 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access strobe configuration system and process operable to generate a strobe signal having a selected phase. Based on the strobe signal, a write/read cycle using a first logic value at a memory location of a memory device generates a result logic value. The result logic value provided by the write/read cycle is compared to the first logic value. Where there is a mismatch between the result logic value and the first logic value, the phase of the strobe signal is updated. The process is then repeated using a strobe signal having the updated phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.