Scaler architecture for image and video processing
US8009729B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Feb 22, 2006 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Dec 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/85
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This disclosure describes a scaler architecture for image and/or video processing. One aspect relates to an apparatus comprising an image processing unit, a memory, and a coder. The memory is configured to store processed image data from the image processing unit. The coder is configured to retrieve the stored, processed image data from the memory. The coder comprises a scaler configured to upscale the retrieved image data from the memory. The coder is configured to encode the scaled image data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.