Method and apparatus for equalizing a high speed serial data link
US8009763B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2008 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Apr 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03343
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for equalizing a reflection in a reflective high speed serial link. The method involves obtaining an amplitude and delay time of a compensating pulse that is transmitted in response to a pulse transmitted on the serial link. The apparatus comprises a programmable delay element and a driver stage configured to transmit a delayed and amplitude adjusted version of a pulse transmitted on the serial link. A method for equalizing a plurality of reflections in a reflective high speed serial link. The method involves obtaining an amplitude and delay time of a first compensating pulse and an amplitude and delay time of a second compensating pulse. The method further involves transmitting the first compensating and second compensating pulses in response to a pulse transmitted on the serial link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.