Clock embedded differential data receiving system for ternary lines differential signaling
US8009784B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2008 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Jul 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.