Pattern matching technique for high throughput network processing
US8010481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2007 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Dec 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/74591
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A pattern matching technique for high throughput network processing includes a simple yet powerful special purpose architecture and a set of novel string matching algorithms that can work in unison. The novel set of algorithms allow for bit-level partitioning of rules such that may be more easily implemented in hardware or software. The result is a device that maintains tight worst case bounds on performance, can be updated with new rules without interrupting operation, compiles in seconds instead of hours, and is ten times more efficient than the existing best known solutions in this area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.