Parallelizing sequential frameworks using transactions
US8010550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2007 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Jun 3, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/467
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various technologies and techniques are disclosed for transforming a sequential loop into a parallel loop for use with a transactional memory system. A transactional memory system is provided. A first section of code containing an original sequential loop is transformed into a second section of code containing a parallel loop that uses transactions to preserve an original input to output mapping. For example, the original sequential loop can be transformed into a parallel loop by taking each iteration of the original sequential loop and generating a separate transaction that follows a pre-determined commit order process. At least some of the separate transactions are executed in different threads. When an unhandled exception is detected that occurs in a particular transaction while the parallel loop is executing, state modifications made by the particular transaction and predecessor transactions are committed, and state modifications made by successor transactions are discarded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.