Semiconductor memory device and method for controlling clock latency according to reordering of burst data
US8010765B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2007 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Feb 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.