Hardware recovery responsive to concurrent maintenance
US8010838B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2008 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Sep 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a computer implemented method, data processing system, and apparatus to respond to detection of a hardware interface error on a system bus, for example, during a concurrent maintenance operation. The service processor may receive an error on the system bus. The error identifies at least one field replaceable unit and may inhibit the suppression of clock signal to the field replaceable unit. The service processor adds an identifier of the field replaceable unit to an eligible Field Replaceable Unit (FRU) list. The service processor recursively adds at least one field replaceable unit that the field replaceable unit depends upon. The service processor suppresses the clock signal to the field replaceable unit. The service processor inhibits tagging the field replaceable unit as unusable for next initial program load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.