Patent · US Active

Method and apparatus for generating layout regions with local preferred directions

US8010929B2 · kind B2 · utility

10Cited by

76References

19Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Anish Malhotra · San Jose, US
Jonathan Frankle · Los Gatos, US
Asmus Hetzel · Berlin, DE

Key dates

Filing date	Mar 24, 2010
Grant date	Aug 30, 2011
Priority date	—
Expiry date	Mar 24, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/394
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Some embodiments of the invention provide a method for defining wiring directions in a design layout having several wiring layers. The method decomposes a first wiring layer into several non-overlapping regions. It assigns at least two different local preferred wiring directions to at least two of the regions. In some embodiments, the method decomposing the first wiring layer by using the vertices of items in the layout to decompose the layout. In some of these embodiments, the items include macro blocks. The method of some embodiments also identifies several power via arrays on the first wiring layer, and identifies a local preferred wiring direction based on the arrangement of the power via arrays on the first wiring layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.