Tool for a configurable integrated circuit that uses determination of dynamic power consumption
US8010931B1 · kind B1 · utility
3Cited by
15References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2007 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Mar 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configurable logic tool that allows minimization of dynamic power within an FPGA design without changing user-entered specifications. The minimization of power may use minimized clock nets as a first order operation, and a second order operation that minimizes other factors, such as area of placement, area of clocks and/or slack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.