Semiconductor device having a junction of P type pillar region and N type pillar region
US8013360B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2010 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Apr 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/146
Abstract
A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.