Thin double-sided package substrate and manufacture method thereof
US8013434B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2008 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Dec 20, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a package substrate comprising an insulative carrier having a through-hole penetrating the top and bottom surfaces thereof; at least one first and second conductive layers comprising circuits respectively formed on the top and bottom surfaces and covering an opening of the through-hole; a conductive element set in the through-hole for electrically connecting the first and second conductive layers; a first metal layer formed on the first and/or the second conductive layer; and at least one chip receiving bay formed by removing a portion of the carrier from the upper to the lower surfaces until the second conductive layer is exposed for accommodating at least one chip therein on the exposed second conductive layer. The package structure has a reduced overall thickness and an enhanced heat-dissipation effect for the chip and prevents from humidity penetration. A manufacturing method for the package structure is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.