Test handler and loading method thereof
US8013620B2 · kind B2 · utility
2Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2009 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Dec 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2867
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
When a test handler loads semiconductor devices of user trays onto a test tray, the test handler adjusts a front/rear pitch or a right/left pitch between the semiconductor devices, adjusts the right/left pitch or the front/rear pitch, and loads the semiconductor devices. The test handler can sequentially adjust individually the front/rear pitch and the right/left pitch between the semiconductor devices, thereby reducing the apparatus weight and the loading time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.