Circuit substrate for preventing warpage and package using the same
US8014154B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2007 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Apr 27, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a circuit substrate comprises a substrate; and a warpage preventing pattern disposed on the substrate. The warpage preventing pattern comprises a first pattern at a first corner of the substrate and a second pattern at a second corner of the substrate. The first corner and the second corner are disposed adjacent to each other. An overall orientation of the first pattern is different from an overall orientation of the second pattern with respect to the substrate. The warping of a semiconductor package can be significantly reduced by cutting off stress lines in the corners of the circuit substrate. Various configurations and orientations of the warpage preventing pattern are provided in order to effectively block stress concentration in the corners of the circuit substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.