Reduced-power programming of multi-level cell (MLC) memory
US8014196B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2008 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Apr 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log2 m) MLCs are used to store the p-symbol codeword (iii) each MLC stores one symbol of the codeword. The energy-saving decoder is adapted to read p-symbol codewords from the MLC NAND flash memory and decode each p-symbol codeword into a k-bit segment of raw user data for provision to the host controller. The host controller is adapted to vary k and n to conserve usage of power or memory-space, as needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.