Receiver employing selectable A/D sample clock frequency
US8014477B1 · kind B1 · utility
5Cited by
10References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2006 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Feb 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.