Post-execution software debugger with coverage display
US8015552B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2004 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | May 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of validating a testing procedure in a computer program is disclosed. A sequence of machine code instructions performed by a processor is recorded as trace data. Further, a mapping file is accessed. In addition, a source line is translated into a plurality of machine code instructions according to a mapping found in the mapping file. Accordingly, at least a portion of the trace data is searched through to determine whether each machine instruction in the plurality of machine instructions has been executed. An indication is displayed of whether any of the machine instructions in the plurality of machine instructions has been executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.