Method of forming isolation layer structure and method of manufacturing a semiconductor device including the same
US8017495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2010 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Nov 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.