Architecture for local programming of quantum processor elements using latching qubits
US8018244B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2010 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Oct 21, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for a quantum processor may include a set of superconducting flux qubits operated as computation qubits and a set of superconducting flux qubits operated as latching qubits. Latching qubits may include a first closed superconducting loop with serially coupled superconducting inductors, interrupted by a split junction loop with at least two Josephson junctions; and a clock signal input structure configured to couple clock signals to the split junction loop. Flux-based superconducting shift registers may be formed from latching qubits and sets of dummy latching qubits. The devices may include clock lines to clock signals to latch the latching qubits. Thus, latching qubits may be used to program and configure computation qubits in a quantum processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.