Over-voltage tolerant input circuit
US8018268B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 15, 2005 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Jul 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An over-voltage tolerant input circuit has a pad. An Nwell bias circuit is electrically coupled to the pad. A current block circuit is electrically coupled to the Nwell bias circuit. The current block circuit has a control signal coupled to a gate of a transistor in a current path of the Nwell bias circuit. The current block circuit includes a logic gate having a first input coupled to the pad and a second input coupled to an over voltage signal of the Nwell bias circuit. An output of the logic gate is the control signal. An n-type transistor is coupled between the over voltage signal and the first input of the logic gate. A transistor has a gate electrically coupled to the control signal and has a drain coupled to the first input of the logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.