Method of using integrated power amplifier
US8018284B2 · kind B2 · utility
0Cited by
5References
6Claims
0Family size
Inventors
Key dates
| Filing date | Dec 30, 2009 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Jan 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output-impedance in a power amplifier is provided. A first transistor QBUF of a buffer stage is connected to a first side of a resistor RF and a second transistor QAMP to a second opposite side of the resistor RF. The first transistor feeds a current IRF to the second resistor QAMP. The current IRF at the second transistor is copied and multiplied by a factor (n) to form an output current IOUT, as (1+n)*IRF. The current IRF is fed back to the first transistor and the output current IOUT is fed to a load resistor R.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.