Systems and methods for receive and transmission queue processing in a multi-core architecture
US8018961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2009 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Dec 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described herein is a method and system for directing outgoing data packets from packet engines to a transmit queue of a NIC in a multi-core system, and a method and system for directing incoming data packets from a receive queue of the NIC to the packet engines. Packet engines store outgoing traffic in logical transmit queues in the packet engines. An interface module obtains the outgoing traffic and stores it in a transmit queue of the NIC, after which the NIC transmits the traffic from the multi-core system over a network. The NIC receives incoming traffic and stores it in a NIC receive queue. The interface module obtains the incoming traffic and applies a hash to a tuple of each obtained data packet. The interface module then stores each data packet in the logical receive queue of a packet engine on the core identified by the result of the hash.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.