Calibration techniques for frequency synthesizers
US8019301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2008 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Nov 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/199
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.