Pipeline processor with write control and validity flags for controlling write-back of execution result data stored in pipeline buffer register
US8019974B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 12, 2009 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Jul 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bypass circuit is provided in a pipeline processor. A pipeline register is provided between an instruction execution stage and a write-back stage. The pipeline register stores a data validity flag and a WRITE control flag to control writing data into a general purpose register unit. The data retained in the pipeline register is allowed to be written back into the general purpose register unit when the WRITE control flag indicates “valid”. The pipeline register continues to retain the retained data even after the writing of the retained data into the general purpose register unit. The first pipeline register supplies the retained data to the second stage through the bypass circuit at the time of executing a subsequent instruction having data dependency on a preceding instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.