Memory-hazard detection and avoidance instructions for vector processing
US8019976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2007 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Jul 22, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor that is configured to perform parallel operations in a computer system where one or more memory hazards may be present is described. An instruction fetch unit within the processor is configured to fetch instructions for detecting one or more critical memory hazards between memory addresses if memory operations are performed in parallel on multiple addresses corresponding to at least a partial vector of addresses. Note that critical memory hazards include memory hazards that lead to different results when the memory addresses are processed in parallel than when the memory addresses are processed sequentially. Furthermore, an execution unit within the processor is configured to execute the instructions for detecting the one or more critical memory hazards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.