Multiple voltage threshold timing analysis for a digital integrated circuit
US8020129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2008 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Aug 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.