Timing analysis apparatus and method for semiconductor integrated circuit in consideration of power supply and ground noises
US8020130B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2008 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Dec 1, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power supply, decomposes the noise waveform into frequency components, classifies the frequency components into low-frequency components lower than a predetermined threshold frequency and high-frequency components higher than the threshold frequency, calculates a static delay time of each of the logic gates due to the low-frequency components, calculates a dynamic delay time of each of the logic gates due to the high-frequency components, and determines a delay time of each of the logic gates by synthesizing the calculated respective delay times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.