Hardware accelerator
US8020142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2006 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | May 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.