Lithographic process using a nanowire mask, and nanoscale devices fabricated using the process
US8022393B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2008 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Aug 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The disclosure pertains to a method for making a nanoscale filed effect transistor structure on a semiconductor substrate. The method comprises disposing a mask on a semiconductor upper layer of a multi-layer substrate, and removing areas of the upper layer not covered by the mask in a nanowire lithography process. The mask includes two conductive terminals separated by a distance, and a nanowire in contact with the conductive terminals across the distance. The nanowire lithography may be carried out using a deep-reactive-ion-etching, which results in an integration of the nanowire mask and the underlying semiconductor layer to form a nanoscale semiconductor channel for the field effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.