Memory and interconnect design in fine pitch
US8022443B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2008 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Aug 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/48
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a plurality of signal lines. A first signal line layer includes a plurality of first signal lines. A second signal line layer includes a plurality of second signal lines arranged on top of and insulated from the first signal line layer. A third signal line layer includes a plurality of third signal lines arranged on top of and insulated from the second signal line layer. A contact extends through the second signal line layer and connects at least one of the plurality of third signal lines to at least one of the first signal lines. At least one of the second signal lines further extends in a second direction to bend around the contact such that a predetermined distance separates the plurality of second signal lines from the contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.