Semiconductor memory device
US8022484B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2008 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Aug 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.