Patent · US Expired

Electrical component having a reduced substrate area

US8022556B2 · kind B2 · utility

0Cited by

13References

19Claims

0Family size

Assignee

EPCOS AG · DE

Inventors

Peter Selmeier · Haag in Oberbayern, DE
Tobias Krems · Munich, DE

Key dates

Filing date	Dec 16, 2003
Grant date	Sep 20, 2011
Priority date	—
Expiry date	Sep 7, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH03H9/643
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An electrical component includes a substrate, component structures on the substrate, and solder metal platings electrically connected to the component structures. The substrate is electrically and mechanically connected in a flip chip arrangement to a carrier via connections formed by solder bumps. The solder bumps mate to the solder metal platings. At least one of the solder bumps is on a first solder metal plating. The first solder metal plating has first and second dimensions, where the first dimension is larger than the second dimension.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.