Semiconductor device and structure
US8026521B1 · kind B1 · utility
96Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2010 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Oct 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.