Reset signal generating circuit
US8026751B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 25, 2010 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Jan 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reset signal generating circuit for a processor includes a charging circuit, a discharging circuit, and a triggering circuit. The charging circuit receives timing pulse signals from the processor to supply charging current according to the timing pulse signals when the processor operates normally, and stops supplying the charging current when the processor is at fault. The discharging circuit buffers the charging current supplied by the charging circuit when the processor operates normally, and discharges a low voltage to the triggering circuit when the processor is at fault. The triggering circuit outputs a trigger signal to the processor when the triggering circuit detects the low voltage to reset the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.